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PMOS models

P-channel enhancement MOSFET Compare its models in the same order shown in the component inspector.

Symbol

PMOS symbol
Default symbol for a new PMOS component.

Model choice belongs to each placed PMOS component. Changing one component does not change other instances or the default for future placements.

All datasheet fields use positive magnitudes. A PMOS channel turns on as its gate moves below its source.

1

Signal

Square-law channel for bias, gain, and AC, with no intrinsic device charge.

Default
Qualified analyses
  • Operating point
  • DC sweep
  • AC sweep
  • Transient

Model definition

Signal uses a continuous square-law channel. OhmSpice calibrates the channel from threshold voltage and forward transconductance at the stated drain current.

A small fixed output slope keeps drain current dependent on drain voltage, but the model adds no intrinsic capacitances.

Equations

KP=gfs22ID,ref,λ=1ID,ref 100 kΩK_P=\frac{g_{fs}^2}{2I_{D,\mathrm{ref}}},\qquad \lambda=\frac{1}{I_{D,\mathrm{ref}}\,100\,\mathrm{k}\Omega}
The transconductance datum sets channel strength. A fixed 100 kΩ output resistance at the reference current sets channel-length modulation.
VOV=∣VGS∣−VGS(th)V_{\mathrm{OV}}=\lvert V_{GS}\rvert-V_{GS(th)}
PMOS and NMOS use the same positive-magnitude equations after applying device polarity.
ID={0VOV≤0KP ⁣(VOVVDS−VDS22)(1+λVDS)0<VDS<VOVKP2VOV2(1+λVDS)VDS≥VOVI_D=\begin{cases}0&V_{\mathrm{OV}}\leq0\\K_P\!\left(V_{\mathrm{OV}}V_{DS}-\frac{V_{DS}^2}{2}\right)(1+\lambda V_{DS})&0<V_{DS}<V_{\mathrm{OV}}\\\frac{K_P}{2}V_{\mathrm{OV}}^2(1+\lambda V_{DS})&V_{DS}\geq V_{\mathrm{OV}}\end{cases}
The native Level-1 channel uses cutoff, triode, and square-law saturation regions.

Parameters

ParameterDefaultAccepted values
VGS(th)Gate-source threshold magnitude; the polarity applies its sign.1.5 VGreater than 0
Forward transconductanceForward transconductance (gfs) at the stated drain current.20 mS; at ID 10 mAGreater than 0; reference condition greater than 0

Limits

  • No gate, Miller, or output capacitance is included.
  • No body-diode calibration, breakdown, avalanche, temperature, or noise behavior is included.
  • Intrinsic frequency roll-off must come from external components.
2

Power

Fast switch-level channel with finite RDS(on) and charge-free body-diode conduction.

Qualified analyses
  • Operating point
  • DC sweep
  • Transient

Model definition

Power is a fast system-level switch for converter, modulation, and control simulation. The channel changes between the entered RDS(on) and a fixed 1 GΩ off resistance at the gate threshold.

A separate charge-free, piecewise-linear body path uses the entered forward point. NMOS uses VGS and source-to-drain body conduction; PMOS applies the corresponding reversed polarities.

Equations

Rch={RDS(on),VGS>VGS(th)1 GΩ,VGS<VGS(th)R_{ch}=\begin{cases}R_{DS(on)},&V_{GS}>V_{GS(th)}\\1\,\mathrm{G}\Omega,&V_{GS}<V_{GS(th)}\end{cases}
For NMOS, the gate-source command selects the on or off channel resistance. PMOS uses the equivalent source-gate command.
Ich=VDSRch,VH=50 mVI_{ch}=\frac{V_{DS}}{R_{ch}},\qquad V_H=50\,\mathrm{mV}
The conducting channel is resistive rather than a square-law semiconductor. A small fixed hysteresis prevents chatter at threshold.
RB=RDS(on)2,VK=VF−IFRBR_B=\frac{R_{DS(on)}}{2},\qquad V_K=V_F-I_F R_B
The body-path slope is half the selected channel on resistance. The entered forward point sets its voltage knee.
IB=max⁡ ⁣(VAK−VKRB,0)I_B=\max\!\left(\frac{V_{AK}-V_K}{R_B},0\right)
The body path conducts linearly above its calibrated knee and stores no charge.

Parameters

ParameterDefaultAccepted values
VGS(th)Gate-source threshold magnitude; the polarity applies its sign.3 VGreater than 0
RDS(on)On-state drain-source resistance while the gate command is on.50 mΩGreater than 0
Body diode VfBody-diode forward voltage at the stated current.0.8 V; at current 1 AGreater than 0; reference condition greater than 0

Limits

  • Channel saturation, transconductance behavior, gate charge, Miller plateau, and output capacitance are omitted.
  • The body path has no junction capacitance, stored charge, or reverse recovery.
  • Breakdown, avalanche, leakage, temperature, and package inductance are omitted. Use Switching or a qualified vendor model for device edges and switching-loss estimates.
  • AC analysis is not qualified for this piecewise-linear system model.
3

Switching

Detailed generic semiconductor with gate and Miller charge, internal gate resistance, channel saturation, and body-diode recovery.

Qualified analyses
  • Operating point
  • DC sweep
  • AC sweep
  • Transient

Model definition

Switching retains the Power conduction and reverse-path behavior, then adds gate charge, Miller charge, internal gate resistance, and body-diode recovery.

OhmSpice derives constant effective gate-source, gate-drain, and drain-source capacitances from the entered charge and output-energy data.

Equations

KP=2ID,plateau(Vplateau−VGS(th))2K_P=\frac{2I_{D,\mathrm{plateau}}}{\left(V_{\mathrm{plateau}}-V_{GS(th)}\right)^2}
The plateau point calibrates channel transconductance.
Rch,ref=1KP(VGS,ref−VGS(th)),RD=RDS(on)−Rch,refR_{\mathrm{ch,ref}}=\frac{1}{K_P(V_{GS,\mathrm{ref}}-V_{GS(th)})},\qquad R_D=R_{DS(on)}-R_{\mathrm{ch,ref}}
The VDMOS drain resistance supplies the remaining on resistance at the stated gate drive.
Ceff=CossorCeff=2EossVDS2C_{\mathrm{eff}}=C_{oss}\quad\text{or}\quad C_{\mathrm{eff}}=\frac{2E_{oss}}{V_{DS}^2}
The selected output datum becomes one constant energy-equivalent capacitance.
Cgd=QgdVDS,Cgs=QgsVplateau−Cgd,Cds=Ceff−CgdC_{gd}=\frac{Q_{gd}}{V_{DS}},\quad C_{gs}=\frac{Q_{gs}}{V_{\mathrm{plateau}}}-C_{gd},\quad C_{ds}=C_{\mathrm{eff}}-C_{gd}
Datasheet charge values become constant effective capacitances.
RB=RDS(on)2,IS,body=IFexp⁡ ⁣(VF−IFRBVT)−1,τrr=QrrIFR_B=\frac{R_{DS(on)}}{2},\quad I_{S,\mathrm{body}}=\frac{I_F}{\exp\!\left(\frac{V_F-I_F R_B}{V_T}\right)-1},\quad \tau_{rr}=\frac{Q_{rr}}{I_F}
Body-diode resistance, saturation current, and transit time reproduce the forward and recovery reference points.
VRG=RGIG,VLS=LSdISdtV_{RG}=R_G I_G,\qquad V_{LS}=L_S\frac{\mathrm dI_S}{\mathrm dt}
The selected internal gate resistance and optional source inductance are explicit series elements.

Parameters

ParameterDefaultAccepted values
VGS(th)Gate-source threshold magnitude; the polarity applies its sign.3 VGreater than 0
RDS(on)On-state drain-source resistance at the stated gate drive.50 mΩ; at VGS 10 VGreater than 0; reference condition greater than 0
Gate plateau voltageMiller plateau voltage at the stated drain current.5 V; at ID 10 AGreater than 0; reference condition greater than 0
Gate-source chargeGate charge accumulated from zero volts to the Miller plateau (Qgs).20 nCGreater than 0
Gate-drain chargeMiller charge (Qgd) at the stated drain voltage.10 nC; at VDS 100 VGreater than 0; reference condition greater than 0
Internal gate resistanceEffective series resistance inside the gate terminal.2 ΩGreater than 0
Output dataWhether the output datum is entered as an effective output capacitance or a stored output energy.Coss @ VDSCoss @ VDS, Eoss @ VDS
Effective CossConstant effective output capacitance at the stated drain voltage.Shown when Output data is Coss @ VDS.200 pF; at VDS 100 VGreater than 0; reference condition greater than 0
EossStored output energy at the stated drain voltage; Ceff = 2·Eoss / VDS².Shown when Output data is Eoss @ VDS.1 µJ; at VDS 100 VGreater than 0; reference condition greater than 0
Body diode VfBody-diode forward voltage at the stated current.0.8 V; at current 1 AGreater than 0; reference condition greater than 0
Body-diode QrrBody-diode reverse-recovery charge at the stated prior forward current.100 nC; at IF 1 AGreater than 0; reference condition greater than 0
Source inductanceOptional package/layout source-lead inductance; 0 omits it.0 nHAt least 0

Limits

  • Capacitances remain constant approximations rather than voltage-dependent charge curves.
  • Recovery softness, avalanche, breakdown, temperature, and detailed package parasitics are omitted.
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