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Inverter models

Reverses the input logic level Compare its models in the same order shown in the component inspector.

Symbol

Inverter symbol
Default symbol for a new Inverter component.

Model choice belongs to each placed Inverter component. Changing one component does not change other instances or the default for future placements.

1

Ideal

Rail-to-rail ideal logic with a 50% input threshold and negligible delay.

Default
Qualified analyses
  • Operating point
  • DC sweep
  • Transient

Model definition

The Ideal model evaluates the selected truth table from analog input voltages and drives the output to the VDD or VSS rail.

Each input switches at the midpoint between the supply rails, with negligible propagation delay and no input loading.

Equations

xi={1,Vi>VSS+0.5(VDD−VSS)0,otherwisex_i=\begin{cases}1,&V_i>V_{SS}+0.5(V_{DD}-V_{SS})\\0,&\text{otherwise}\end{cases}
Every analog input becomes a logic value at the 50% supply threshold.
VOUT={VDD,f(x1,…,xn)=1VSS,f(x1,…,xn)=0V_{OUT}=\begin{cases}V_{DD},&f(x_1,\ldots,x_n)=1\\V_{SS},&f(x_1,\ldots,x_n)=0\end{cases}
The selected gate function drives the output directly to a supply rail.

Parameters

This model has no editable model parameters.

Limits

  • Input loading, finite output resistance, propagation delay, and finite edge time are omitted.
  • Static supply current, clamp diodes, and analog behavior at the threshold are omitted.
  • AC analysis is not qualified for the event-driven logic behavior.
2

Timed

Supply-relative thresholds, asymmetric propagation delay, finite output edges, input capacitance, and output resistance.

Qualified analyses
  • Operating point
  • DC sweep
  • Transient

Model definition

The Timed model evaluates the selected truth table with supply-relative low and high thresholds, then applies separate rising and falling delays and finite output edges.

Input capacitance loads each logic input, and output resistance models finite drive strength.

Equations

VIL=VSS+rL(VDD−VSS),VIH=VSS+rH(VDD−VSS)V_{IL}=V_{SS}+r_L(V_{DD}-V_{SS}),\qquad V_{IH}=V_{SS}+r_H(V_{DD}-V_{SS})
Low and high thresholds track the actual supply rails. The band between them is undefined.
VOUT→VSS or VDDafter tPHL or tPLHV_{OUT}\rightarrow V_{SS}\ \text{or}\ V_{DD}\quad\text{after }t_{PHL}\ \text{or}\ t_{PLH}
The truth-table result selects a rail after the corresponding propagation delay and transition time.

Parameters

ParameterDefaultAccepted values
Input low thresholdMaximum low input as a fraction of VDD−VSS; it must stay below the high threshold.30 %At least 0 and at most 1
Input high thresholdMinimum high input as a fraction of VDD−VSS; the band between thresholds is undefined.70 %At least 0 and at most 1
Propagation delay low→highDigital event delay before a rising output transition.10 nsGreater than 0
Propagation delay high→lowDigital event delay before a falling output transition.10 nsGreater than 0
Rise timeAnalog output transition time from the low rail to the high rail.5 nsGreater than 0
Fall timeAnalog output transition time from the high rail to the low rail.5 nsGreater than 0
Input capacitanceCapacitance from each signal input to VSS.5 pFAt least 0
Output resistanceSeries resistance of the push-pull output driver.50 ΩGreater than 0

Limits

  • Thresholds and delays do not vary with temperature, supply voltage, or output load.
  • Static supply current, clamp diodes, metastability, and detailed input analog behavior are omitted.
  • AC analysis is not qualified for the event-driven logic behavior.
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