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Powered Op Amp models

With positive and negative supply pins Compare its models in the same order shown in the component inspector.

Symbol

Powered Op Amp symbol
Default symbol for a new Powered Op Amp component.

Model choice belongs to each placed Powered Op Amp component. Changing one component does not change other instances or the default for future placements.

1

Rails

Effectively infinite gain and bandwidth with an output limited inside the connected supply rails.

Default
Qualified analyses
  • Operating point
  • DC sweep
  • AC sweep
  • Transient

Model definition

Rails uses a very high-gain differential stage and limits its output between the connected supply rails minus the selected headroom.

It preserves fast idealized feedback behavior while making saturation visible.

Equations

Vraw=A0(V+−V−),A0=106V_{\mathrm{raw}}=A_0(V_+-V_-),\qquad A_0=10^6
A one-million-gain differential stage drives the internal output node.
Vlim=clip⁡ ⁣(Vraw,VEE+H,VCC−H)V_{\mathrm{lim}}=\operatorname{clip}\!\left(V_{\mathrm{raw}},V_{EE}+H,V_{CC}-H\right)
Self-controlled switches clamp the internal node to the selected rail headroom.
Rin=1 TΩ,Rout=10 mΩ,Rclamp,on=1 mΩR_{\mathrm{in}}=1\,\mathrm T\Omega,\quad R_{\mathrm{out}}=10\,\mathrm{m}\Omega,\quad R_{\mathrm{clamp,on}}=1\,\mathrm{m}\Omega
These fixed resistances regularize the input, output, and rail clamps; clamp hysteresis is 1 mV.

Parameters

ParameterDefaultAccepted values
Output headroomOutput saturation margin from each supply rail.1 VAt least 0

Limits

  • The clamp can settle within about 20 mV of the configured limit because of numerical regularization.
  • Finite bandwidth, slew rate, offset, bias current, common-mode limits, current limit, noise, CMRR, and PSRR are omitted.
2

Single-pole

Unity-gain-stable dominant-pole macromodel with slew and headroom limits.

Qualified analyses
  • Operating point
  • DC sweep
  • AC sweep
  • Transient

Model definition

Single-pole adds finite DC gain and a dominant pole chosen from gain-bandwidth product. It limits the internal charging current to enforce the selected slew rate.

The output remains limited inside the connected rails by the selected headroom.

Equations

Rp=100 kΩ,gm=A0Rp,Cp=A02πRp GBWR_p=100\,\mathrm{k}\Omega,\qquad g_m=\frac{A_0}{R_p},\qquad C_p=\frac{A_0}{2\pi R_p\,\mathrm{GBW}}
A fixed pole resistance and derived transconductance and capacitance produce the selected DC gain and gain-bandwidth product.
Imax⁡=SR Cp,Ip=Imax⁡tanh⁡ ⁣(gm(V+−V−)Imax⁡)I_{\max}=\mathrm{SR}\,C_p,\qquad I_p=I_{\max}\tanh\!\left(\frac{g_m(V_+-V_-)}{I_{\max}}\right)
The differential transconductor is linear near zero and smoothly limited to the current required for the selected slew rate.
CpdVrawdt+VrawRp=Ip,A(s)=A01+sA0/(2π GBW)C_p\frac{\mathrm dV_{\mathrm{raw}}}{\mathrm dt}+\frac{V_{\mathrm{raw}}}{R_p}=I_p,\qquad A(s)=\frac{A_0}{1+sA_0/(2\pi\,\mathrm{GBW})}
The pole-node differential equation gives the single-pole open-loop transfer function.
Vlim=clip⁡(Vraw,VEE+H,VCC−H),Rout=10 mΩV_{\mathrm{lim}}=\operatorname{clip}(V_{\mathrm{raw}},V_{EE}+H,V_{CC}-H),\qquad R_{\mathrm{out}}=10\,\mathrm{m}\Omega
The output is clipped to the selected headroom and connected through a fixed output resistance.

Parameters

ParameterDefaultAccepted values
Open-loop gainDC open-loop voltage gain.100,000 V/VGreater than 1
Gain-bandwidth productUnity-gain bandwidth; sets the dominant pole with open-loop gain.1 MHzGreater than 0
Slew rateMaximum output rate of change.0.5 V/µsGreater than 0
Output headroomOutput saturation margin from each supply rail.1 VAt least 0

Limits

  • The response is symmetric, single-pole, and noiseless.
  • Offset, bias current, common-mode limits, current limiting, overload recovery, CMRR, and PSRR are omitted.
3

Multipole

Datasheet-fitted two-pole amplifier with finite output resistance, input capacitance, slew, and headroom limits.

Qualified analyses
  • Operating point
  • DC sweep
  • AC sweep
  • Transient

Model definition

Multipole retains the finite-gain, slew-limited dominant stage and adds a second pole inferred from the entered unity-gain frequency.

Input common-mode and differential capacitance, finite output resistance, and rail headroom make load and feedback-network interactions part of the simulated loop response.

Equations

fp1=GBWA0,A(s)=A0(1+s/(2πfp1))(1+s/(2πfp2))f_{p1}=\frac{\mathrm{GBW}}{A_0},\qquad A(s)=\frac{A_0}{(1+s/(2\pi f_{p1}))(1+s/(2\pi f_{p2}))}
The dominant pole comes from DC gain and gain-bandwidth product; the second pole is selected so the two-pole magnitude reaches unity at the entered unity-gain frequency.
Imax⁡=SR Cp1,Ip=Imax⁡tanh⁡ ⁣(gm(V+−V−)Imax⁡)I_{\max}=\mathrm{SR}\,C_{p1},\qquad I_p=I_{\max}\tanh\!\left(\frac{g_m(V_+-V_-)}{I_{\max}}\right)
The dominant-stage current limit produces the selected symmetric slew rate.
CCM:V+ ⁣→VEE, V− ⁣→VEE;CDIFF:V+ ⁣↔V−C_{CM}: V_+\!\to V_{EE},\ V_-\!\to V_{EE};\qquad C_{DIFF}: V_+\!\leftrightarrow V_-
The entered common-mode and differential capacitances load the external source and feedback network explicitly.
Vlim=clip⁡(Vraw,VEE+H,VCC−H),Vout=Vlim−IoutRoutV_{\mathrm{lim}}=\operatorname{clip}(V_{\mathrm{raw}},V_{EE}+H,V_{CC}-H),\qquad V_{\mathrm{out}}=V_{\mathrm{lim}}-I_{\mathrm{out}}R_{\mathrm{out}}
Rail headroom limits the internal target while the entered output resistance creates load-dependent output error.

Parameters

ParameterDefaultAccepted values
Open-loop gainDC open-loop voltage gain.100,000 V/VGreater than 1
Gain-bandwidth productDatasheet gain-bandwidth product used to set the dominant pole.1 MHzGreater than 0
Unity-gain frequencyDatasheet open-loop 0 dB crossover. The model derives its internal high-frequency roll-off from this value, DC gain, and GBW. Use the GBW value when the datasheet specifies only one; must not exceed GBW.0.98 MHzGreater than 0
Slew rateSymmetric maximum output rate of change.0.5 V/µsGreater than 0
Open-loop output resistanceSmall-signal series resistance of the output stage before feedback reduces closed-loop impedance.50 ΩGreater than 0
Input common-mode capacitanceCapacitance from each input to the negative supply reference.5 pFAt least 0
Input differential capacitanceCapacitance directly between the non-inverting and inverting inputs.2 pFAt least 0
Output headroomOutput saturation margin from each supply rail.1 VAt least 0

Limits

  • The second pole is inferred from scalar GBW and unity-gain-frequency inputs rather than a full measured open-loop response.
  • Offset, bias current, current limiting, noise, CMRR and PSRR roll-off, overload recovery, and temperature drift are omitted.
4

Practical

Single-pole amplifier with datasheet DC errors, input/output ranges, loaded swing, current limit, and quiescent current.

Qualified analyses
  • Operating point
  • DC sweep
  • AC sweep
  • Transient

Model definition

Practical retains the Single-pole gain, bandwidth, slew, and rail behavior. It adds input offset and bias current, input common-mode limits, loaded output swing, symmetric current limiting, and quiescent supply current.

The output stage is calibrated so the entered headroom occurs at its stated load current, then smoothly approaches the selected current limit.

Equations

V±′=clip⁡(V±,VEE+HL,VCC−HH),Vd′=V+′−V−′+VOSV_\pm'=\operatorname{clip}(V_\pm,V_{EE}+H_L,V_{CC}-H_H),\qquad V_d'=V_+'-V_-'+V_{OS}
Each input is clipped to the common-mode window before input offset is applied.
Rp=100 kΩ,gm=A0Rp,Cp=A02πRp GBW,Imax⁡=SR CpR_p=100\,\mathrm{k}\Omega,\quad g_m=\frac{A_0}{R_p},\quad C_p=\frac{A_0}{2\pi R_p\,\mathrm{GBW}},\quad I_{\max}=\mathrm{SR}\,C_p
The gain stage uses the same calibrated single-pole and slew-limited core.
CpdVrawdt+VrawRp=Imax⁡tanh⁡ ⁣(gmVd′Imax⁡)C_p\frac{\mathrm dV_{\mathrm{raw}}}{\mathrm dt}+\frac{V_{\mathrm{raw}}}{R_p}=I_{\max}\tanh\!\left(\frac{g_mV_d'}{I_{\max}}\right)
This differential equation defines finite gain, bandwidth, slew rate, and offset response.
Ro=HoutIlimatanh⁡(Iref/Ilim)R_o=\frac{H_{\mathrm{out}}}{I_{\mathrm{lim}}\operatorname{atanh}(I_{\mathrm{ref}}/I_{\mathrm{lim}})}
The loaded output-swing point determines the soft output-stage resistance.
Vlim=clip⁡(Vraw,VEE,VCC),ΔVsrc=uramp⁡(Vlim−Vout),ΔVsink=uramp⁡(Vout−Vlim)V_{\mathrm{lim}}=\operatorname{clip}(V_{\mathrm{raw}},V_{EE},V_{CC}),\quad \Delta V_{\mathrm{src}}=\operatorname{uramp}(V_{\mathrm{lim}}-V_{\mathrm{out}}),\quad \Delta V_{\mathrm{sink}}=\operatorname{uramp}(V_{\mathrm{out}}-V_{\mathrm{lim}})
The output target is rail-limited. Each drive branch sees only its positive voltage error.
Isrc/sink=Ilimtanh⁡ ⁣(ΔVsrc/sinkIlimRo),0≤Isrc/sink<IlimI_{\mathrm{src/sink}}=I_{\mathrm{lim}}\tanh\!\left(\frac{\Delta V_{\mathrm{src/sink}}}{I_{\mathrm{lim}}R_o}\right),\qquad 0\leq I_{\mathrm{src/sink}}<I_{\mathrm{lim}}
Separate source and sink branches apply the same smooth current limit.
I+=I−=IB,ICC=IQ,Rout=10 mΩI_+=I_-=I_B,\qquad I_{CC}=I_Q,\qquad R_{\mathrm{out}}=10\,\mathrm{m}\Omega
The two input bias currents and the quiescent supply current are explicit sources.

Parameters

ParameterDefaultAccepted values
Open-loop gainDC open-loop voltage gain.100,000 V/VGreater than 1
Gain-bandwidth productUnity-gain bandwidth.1 MHzGreater than 0
Slew rateSymmetric maximum output rate of change.0.5 V/µsGreater than 0
Input offset voltageSigned input-referred offset voltage.1 mVAny finite value
Input bias currentSigned current flowing into each input pin.10 nAAny finite value
Input range from V−Lower input common-mode limit above the negative supply.1 VAt least 0
Input range from V+Upper input common-mode limit below the positive supply.1 VAt least 0
Output headroomOutput distance from either rail at the stated source or sink current.1 V; at |IOUT| 10 mAGreater than 0; reference condition greater than 0
Output current limitSymmetric source and sink current limit.20 mAGreater than 0
Quiescent currentNo-load supply current drawn from V+ to V−.1 mAGreater than 0

Limits

  • Slew and output drive are symmetric.
  • Noise, frequency-shaped CMRR or PSRR, input capacitance, phase reversal, overload recovery, and temperature drift are omitted.
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