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Comparator models

With positive and negative supply pins Compare its models in the same order shown in the component inspector.

Symbol

Comparator symbol
Default symbol for a new Comparator component.

Model choice belongs to each placed Comparator component. Changing one component does not change other instances or the default for future placements.

1

Ideal

Stateful threshold comparison with a hysteresis band; initializes low inside the band.

Default
Qualified analyses
  • Operating point
  • DC sweep
  • Transient

Model definition

Ideal compares the two inputs with a stateful hysteresis band. A rising differential input crosses the upper threshold; a falling input crosses the lower threshold.

The output switches between the connected negative and positive supply rails. If the input starts inside the band, the output initializes low.

Equations

Vd=V+−V−,VLH=VH2,VHL=−VH2V_d=V_+-V_-,\qquad V_{\mathrm{LH}}=\frac{V_H}{2},\qquad V_{\mathrm{HL}}=-\frac{V_H}{2}
The Hysteresis field is the total width of the input switching band.
q+={1Vd≥VLH0Vd≤VHLqVHL<Vd<VLHq^+=\begin{cases}1&V_d\geq V_{\mathrm{LH}}\\0&V_d\leq V_{\mathrm{HL}}\\q&V_{\mathrm{HL}}<V_d<V_{\mathrm{LH}}\end{cases}
The comparator retains its previous state inside the hysteresis band and initializes low.
Vout=VEE+(VCC−VEE)q,Rout=10 mΩV_{\mathrm{out}}=V_{EE}+(V_{CC}-V_{EE})q,\qquad R_{\mathrm{out}}=10\,\mathrm{m}\Omega
The state drives the output to the corresponding supply rail through a fixed output resistance.

Parameters

ParameterDefaultAccepted values
HysteresisTotal input hysteresis band width.10 mVAt least 0

Limits

  • Propagation delay, offset, common-mode range, loaded output levels, supply current, input noise, and output edge rate are omitted.
  • AC sweep is not qualified.
2

Timed

Hysteretic comparator with offset, input range, asymmetric propagation delay, loaded output levels, and supply current.

Qualified analyses
  • Operating point
  • DC sweep
  • Transient

Model definition

Timed retains the hysteretic state machine and adds input offset, common-mode limiting, separate low-to-high and high-to-low delays, loaded output levels, and quiescent current.

Push-pull drives both output states. Open-drain provides only the low-side path, so the circuit must supply an external pull-up.

Equations

V±′=clip⁡(V±,VEE+HL,VCC−HH),Vd′=V+′−V−′+VOSV_\pm'=\operatorname{clip}(V_\pm,V_{EE}+H_L,V_{CC}-H_H),\qquad V_d'=V_+'-V_-'+V_{OS}
Common-mode limiting and offset produce the voltage applied to the hysteretic state machine.
qraw+={1Vd′≥VH/20Vd′≤−VH/2qrawotherwiseq_{\mathrm{raw}}^+=\begin{cases}1&V_d'\geq V_H/2\\0&V_d'\leq -V_H/2\\q_{\mathrm{raw}}&\text{otherwise}\end{cases}
The raw comparison state retains its prior value inside the input hysteresis band.
CD=1 nF,R↑=tpLHln⁡(2)CD,R↓=tpHLln⁡(2)CDC_D=1\,\mathrm{nF},\qquad R_{\uparrow}=\frac{t_{pLH}}{\ln(2)C_D},\qquad R_{\downarrow}=\frac{t_{pHL}}{\ln(2)C_D}
Independent RC paths cross the 0.5 logic threshold at the selected low-to-high and high-to-low delays.
CDdvDdt=qraw−vDR↑ or ↓,q=u(vD−0.5)C_D\frac{\mathrm dv_D}{\mathrm dt}=\frac{q_{\mathrm{raw}}-v_D}{R_{\uparrow\ \mathrm{or}\ \downarrow}},\qquad q=u(v_D-0.5)
The active rise or fall path charges the delay node toward the raw state; the delayed logic state changes at one half.
RL=VOLIOL,RH=VOH,headroomIOHR_L=\frac{V_{OL}}{I_{OL}},\qquad R_H=\frac{V_{OH,\mathrm{headroom}}}{I_{OH}}
The loaded output-level points calibrate the low and push-pull high output resistances.
Rout(q)={RL to VEEq=0RH to VCCq=1 and push-pullopenq=1 and open-drainR_{\mathrm{out}}(q)=\begin{cases}R_L\ \text{to}\ V_{EE}&q=0\\R_H\ \text{to}\ V_{CC}&q=1\ \text{and push-pull}\\\text{open}&q=1\ \text{and open-drain}\end{cases}
The selected output type controls whether a high-side drive path exists.
ICC=IQ,Rseries,out=10 mΩI_{CC}=I_Q,\qquad R_{\mathrm{series,out}}=10\,\mathrm{m}\Omega
Quiescent current and the small series output resistance are explicit circuit elements.

Parameters

ParameterDefaultAccepted values
HysteresisTotal input hysteresis band width.10 mVAt least 0
Input offset voltageSigned input-referred switching offset.1 mVAny finite value
Input range from V−Lower input common-mode limit above the negative supply.0.2 VAt least 0
Input range from V+Upper input common-mode limit below the positive supply.0.2 VAt least 0
Propagation delay low→highDelay from a rising input threshold crossing to the output midpoint.100 nsGreater than 0
Propagation delay high→lowDelay from a falling input threshold crossing to the output midpoint.100 nsGreater than 0
Output typeChoose the datasheet output-stage type.Push-pullPush-pull, Open-drain
Output low voltageLow-state voltage above V− at the stated sink current.0.2 V; at IOL 10 mAGreater than 0; reference condition greater than 0
Output high headroomHigh-state distance below V+ at the stated source current.Shown when Output type is Push-pull.0.2 V; at IOH 10 mAGreater than 0; reference condition greater than 0
Quiescent currentNo-load supply current drawn from V+ to V−.100 µAGreater than 0

Limits

  • Delay does not vary with input overdrive or source impedance.
  • Output edge rate, input bias, kickback, noise, and temperature are omitted.
  • AC sweep is not qualified.
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